Huawei is a leading telecom solutions provider. Through continuous customer-centric innovation, Huawei has established end-to-end advantages in Telecom Network Infrastructure, Application & Software, Professional Services and Devices. With comprehensive strengths in wireline, wireless and IP technologies, Huawei has gained a leading position in the All-IP convergence age. Its products and solutions have been deployed in over 100 countries and have served 45 of the world's top 50 telecom operators, as well as one third of the world's population.

Our Huawei R&D teams develop next generation RF transceivers, supporting 4G (LTE) and 5G systems.

Today, we're seeking team players and technical leaders who get things done and share a passion for bringing new wireless technologies to the rapidly growing mobile market. Now is your chance to join the engineering team and develop new, world-leading products.

Assignment Description

We are offering a long-term SENIOR DIGITAL IC DESIGN ENGINEER (FRONT-END) position enabling you to join the creation of the next generation RF chips.

The Senior Digital IC Design Engineer (Front-End) has the following responsibilities:

• Integrate legacy control and data path designs in new products
• Update and verify legacy designs to fit new product requirements
• Design and verify new ultra-high-speed DSP blocks for next gen products
• Interface with the System Engineer to deeply understand spec requirements and discuss on power trade-offs
• Interface with the physical implementation team for further design and flow improvements

This role includes technical leadership, meaning technical hands-on expertise and excellent team skills; this candidate targets high and challenging standards on technical performance, product and process quality and project schedule.

Required Education and Experience:

• MSEE or equivalent with min 3 to 5y industrial experience in digital FE design
• Good knowledge of Verilog and SystemVerilog for design and verification
• Solid experience with RTL coding and linting
• Knowledgeable about DFT, ATPG and OCC
• Knowledgeable about CDC issues
• Knowledgeable about UPF intents and techniques for low power design
• Experience with delay annotated gatelevel simulation
• Solid grasp of simulation concepts such as regression testing, UVM, functional coverage, assertions, …
• Experience with implementation of high-speed pipelined FIR DSP structures is a plus
• Formal Verification experience is a plus
• Formal lint
• Sequential Equivalence Checking
• Assertion Based Verification
• Experience with C/C++/SystemC models for RTL verification a must
• Python and TCL programming experience a strong plus
• Able to efficiently work in a Linux command line environment as well as in Windows MS Office for reporting and documentation
• Excellent analytical skills
• Good communication skills
• Team-player
• Result driven
• Continuous strive for improvement in circuits and process
• Detail oriented and determined
• Willing to relocate to Leuven (Belgium) region